Fin-type channel transistor and method of manufacturing the same
US7521752B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 21, 2006 |
| Grant date | Apr 21, 2009 |
| Priority date | — |
| Expiry date | Jun 7, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
Abstract
It is possible to reliably implant an impurity into an impurity forming region, and to form a self-aligned silicides on the entire portion of the source and drain regions. There are provided: a first semiconductor layer of a first conductivity type in a substantially a rectangular solid shape formed on a substrate; a gate electrode formed on a pair of first side portions of the first semiconductor layer facing to each other with a gate insulating film being placed between the gate electrode and the first side portions; a second semiconductor layer of the first conductivity type connected to bottom portions of a pair of second side portions of the first semiconductor layer placed in a substantially perpendicular direction with respect to the first side portions, the second semiconductor layer extending along the substantially perpendicular direction; a first impurity region of a second conductivity type formed in the second semiconductor layer; second impurity regions formed on the pair of side portions of the first semiconductor layer and connected to the first impurity region; and a channel region formed between the second impurity regions of the first semiconductor layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.