Semiconductor device
US7521765B2 · kind B2 · utility
11Cited by
3References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 27, 2004 |
| Grant date | Apr 21, 2009 |
| Priority date | — |
| Expiry date | Mar 8, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/49
Abstract
An n-type embedded layer is formed in an N-LV region of a SRAM cell region after an element isolation insulating film is formed on a p-type Si substrate. Thereafter, a p-well and an n-well are formed. In formation of a channel-doped layer, ion implantation is also performed into the N-LV region of the SRAM cell region in parallel with ion implantation into an N-LV of a logic circuit region. Ion-implantation is further performed into the N-LV region of the SRAM cell region in parallel with ion implantation into an N-MV of an I/O region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.