Fifty percent duty cycle clock divider circuit and method
US7521972B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 25, 2007 |
| Grant date | Apr 21, 2009 |
| Priority date | — |
| Expiry date | Oct 8, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K21/10
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a clock divider for producing a signal having a fifty percent duty cycle includes signal modifier circuitry connected to provide a variable clock signal. Responsive to first and second control signals of the signal modifier circuitry having respective first values, the signal modifier circuitry modifies a differential clock signal that includes first and second complementary clock signals to produce the variable clock signal, which contains an extended clock phase in every Ith cycle, I being an integer. The clock divider also contains counting circuitry connected to change the value of an output signal each time I cycles of the variable clock signal are counted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.