Constant margin CMOS biasing circuit
US7522003B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 26, 2006 |
| Grant date | Apr 21, 2009 |
| Priority date | — |
| Expiry date | Dec 26, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/91
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A biasing circuit is presented. The biasing circuit includes a primary biasing circuit, a replica circuit and an amplifier. The primary circuit provides a biasing voltage and a primary voltage. The biasing voltage is the output of the biasing circuit. The replica biasing circuit provides a replica voltage. The replica biasing circuit includes a first resistive element said first resistive element having a resistive characteristics; a first current source said first current source having the first resistive element for generating a current as a function of the first resistive element; a first node to couple to receive the first current source to generate the replica voltage at the first node; a second current source; a second node to coupled to receive the second current source, and a second resistive element coupled between the first noted and the second node, said second resistive element having substantially similar resistive characteristics to that of the first resistive element. The amplifier having a first input terminal to couple to receive the primary voltage from the primary biasing circuit, a second input terminal to couple to receive the replica voltage from the replica b…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.