System and method of coherent data transfer during processor idle states
US7523327B2 · kind B2 · utility
14Cited by
6References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 5, 2005 |
| Grant date | Apr 21, 2009 |
| Priority date | — |
| Expiry date | Jun 24, 2026 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods of managing power provide for placing a processor in a non-snoopable state, where the processor is associated with a system memory. One or more data transfers between a controller and the system memory can be serviced while the processor is in the non-snoopable state. In one embodiment, it is determined that the processor has flushed an internal cache of the processor to the system memory before placing the processor in the non-snoopable state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.