Degeneration technique for designing memory devices
US7523420B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 18, 2006 |
| Grant date | Apr 21, 2009 |
| Priority date | — |
| Expiry date | Apr 18, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system, method and computer program product are provided for producing an instance of a memory device from a banked memory architecture. The banked memory architecture specifies a maximum number of memory banks and a maximum number of rows per memory bank. The method comprises the step of receiving input parameters indicating a number of properties of the memory device, the properties comprising at least a number of rows R for the memory device. Thereafter, a degeneration process is performed on the banked memory architecture in order to produce the instance of a memory device having those properties. The degeneration process comprises the steps of: (i) selecting a number of memory banks B for the instance, where the number is an integer less than or equal to the maximum number of memory banks specified by the banked memory architecture, and B is not constrained to be a factor of R; and (ii) partitioning the number of rows R amongst the selected memory banks such that in each memory bank the number of rows in that memory bank is an integer less than or equal to the maximum number of rows per memory bank specified by the banked memory architecture. This has been found to provide a…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.