Method and system for representing analog connectivity in hardware description language designs
US7523424B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 30, 2005 |
| Grant date | Apr 21, 2009 |
| Priority date | — |
| Expiry date | Nov 22, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
System and method for representing analog connectivity in a design written in a hardware description language are disclosed. The method includes detecting a circuit component that does not have explicit connection path in the design, where the circuit component includes one or more lower-level circuit instances arranged in one or more branches in a hierarchical graph. The method further includes creating one or more instances of the circuit component having at least one additional port than the circuit component, creating one or more ports in the corresponding one or more instances of the circuit component for providing at least an explicit connection path, and representing the design using at least the explicit connection path and the one or more ports of the corresponding one or more instances.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.