Method of eliminating surface stress of silicon wafer
US7524235B2 · kind B2 · utility
1Cited by
11References
17Claims
0Family size
Inventors
Key dates
| Filing date | May 24, 2007 |
| Grant date | Apr 28, 2009 |
| Priority date | — |
| Expiry date | May 24, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/3043
- WIPO fieldOther special machines
- WIPO sectorMechanical engineering
Abstract
This invention provides a method for eliminating the surface stress of a silicon wafer comprising forming one or more anti-stress groove(s) on the surface of the silicon wafer. These anti-stress grooves can reduce or eliminate the surface stress of silicon wafer effectively to avoid the formation of slip lines and dislocation arrangements, which may induce the p-n junction to conduct or the leakage current to increase. The process is highly efficient and low in cost. It is simple to manage and does not require additional equipment beyond that already used for processing of silicon wafers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.