Motor driving circuit having low current consumption under a standby mode
US7525271B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 15, 2007 |
| Grant date | Apr 28, 2009 |
| Priority date | — |
| Expiry date | Jan 10, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02P6/16
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A power cutter, an oscillator, a counter, a S-R latch, and a Hall bias are further disposed inside a DC motor driving circuit so that current consumption of the DC motor driving circuit is reduced significantly under a standby mode. When the counter detects that a received pulse width modulation signal stays at a low electrical level over a predetermined time, the counter triggers the S-R latch so as to activate a disabling signal of the power cutter for shutting down most elements until the pulse width modulation signal returns to a high electrical level. With the aid of the built-in Hall bias, space for externally coupling the Hall bias is saved, and moreover, a Hall sensor retrieves a dynamically-adjusted power and currents so that remarkable current consumption is saved under a standby mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.