Low-power, programmable multi-stage delay cell
US7525356B2 · kind B2 · utility
21Cited by
3References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 14, 2006 |
| Grant date | Apr 28, 2009 |
| Priority date | — |
| Expiry date | Mar 18, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H11/26
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system, apparatus and method for delaying a signal, such as a high-speed signal are disclosed. A multi-stage delay cell is described in which the amount of delay applied to a signal depends on which stages are activated within the cell. In various embodiments of the invention, noise caused by transitions between various delay times within the cell is reduced by efficiently managing voltage states on each of the stages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.