Digital frequency multiplier circuit
US7525393B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 26, 2007 |
| Grant date | Apr 28, 2009 |
| Priority date | — |
| Expiry date | May 24, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0991
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital frequency multiplier circuit is disclosed. The digital frequency multiplier circuit includes a digitally controlled oscillator (DCO), a phase detector and a control circuit. The DCO generates an internal feedback signal. The phase detector detects a phase difference between the internal feedback signal and an external reference clock signal. Coupled between the phase detector and the DCO, the control circuit adjusts the DCO to align the internal feedback signal with the external reference clock signal after a phase difference between the internal feedback signal and the external reference clock signal has been detected. The control circuit also locks a modulation frequency of the DCO and monitors the state of the digital frequency multiplier circuit in order to maintain the lock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.