Memory device and semiconductor integrated circuit
US7525832B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 21, 2006 |
| Grant date | Apr 28, 2009 |
| Priority date | — |
| Expiry date | Aug 1, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/72
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
First electrode layer includes a plurality of first electrode lines (W1, W2) extending parallel to each other. State-variable layer lying on the first electrode layer includes a plurality of state-variable portions (60-11, 60-12, 60-21, 60-22) which exhibits a diode characteristic and a variable-resistance characteristic. Second electrode layer lying on the state-variable layer includes a plurality of second electrode lines (B1, B2) extending parallel to each other. The plurality of first electrode lines and the plurality of second electrode lines are crossing each other when seen in a layer-stacking direction with the state-variable layer interposed therebetween. State-variable portion (60-11) is provided at an intersection of the first electrode line (W1) and the second electrode line (B1) between the first electrode line and the second electrode line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.