Non-imprinting memory with high speed erase
US7525836B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 15, 2008 |
| Grant date | Apr 28, 2009 |
| Priority date | — |
| Expiry date | Apr 15, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F21/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell includes a master cell storing first true/complement data and a slave cell storing second true/complement data. A first circuit associated with the slave cell is operable responsive to a first clock signal to copy first true/complement data from the master cell into the slave cell with same state to be the second true/complement data. A second circuit associated with the master cell is operable response to a second clock signal, which is a non-overlapping complement of the first clock signal, to copy second true/complement data from the slave cell into the master cell with complementary state to be the first true/complement data. A read/write circuit includes circuitry for supporting true/complement data read and write operations with respect to the master cell in either same polarity or opposite polarity state. A state machine tracks polarity state of the first true/complement data so as to control whether a same polarity or opposite polarity state read operation is performed by the read/write circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.