Memory array with pseudo single bit memory cell and method
US7525840B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 7, 2007 |
| Grant date | Apr 28, 2009 |
| Priority date | — |
| Expiry date | Aug 7, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5641
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In the multi level/bit per cell memory array, a flag cell indicates pseudo single bit per cell configuration for one or more cells of the memory array. The output of the cell or cells associated with the flag cell is a single bit when the flag cell is set. The cell or cells associated with the flag cell operate as multi level/bit per cell cells when the flag cell is not set. The flag cell of the memory array may also be a multi level/bit per cell cell that is read to provide a single bit output. Multiple flag cells may be provided and associated with various cells or groups of cells so that these cells or groups of cells may be operated in a user selectable pseudo single bit configuration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.