Method, article, and apparatus for a dynamic phase delay compensator
US7526054B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 4, 2005 |
| Grant date | Apr 28, 2009 |
| Priority date | — |
| Expiry date | Dec 7, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/033
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus, method, and article to dynamically adjust a data signal using a regenerated clock signal in an emulator to increase communication speed between the emulator and the evaluation board is disclosed. In one embodiment, this is achieved by applying a reference clock signal at a predetermined frequency to a digital circuit. A delayed return data signal is then sampled from the digital circuit. The sampled delayed return data signal is then compared to an expected return data signal. The delayed return data signal is then adjusted as a function of the comparison to increase the communication speed between the emulator and the evaluation board.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.