Unified processor cache model in multiprocessor system
US7526611B2 · kind B2 · utility
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Key dates
| Filing date | Mar 22, 2006 |
| Grant date | Apr 28, 2009 |
| Priority date | — |
| Expiry date | Nov 4, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/084
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Exemplary embodiments include a multiprocessor system including: a plurality of processors in operable communication with an address manager and an memory controller; and a unified cache in operable communication with the address manager, wherein the unified cache includes: a plurality of cache addresses; a cache data corresponding to each cache address; a data mask corresponding to each cache data; a plurality of cache agents corresponding to each cache address; and a cache state corresponding to each cache agent.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.