Probabilistic error correction in multi-bit-per-cell flash memory
US7526715B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 26, 2006 |
| Grant date | Apr 28, 2009 |
| Priority date | — |
| Expiry date | Oct 8, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0409
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Data that are stored in cells of a multi-bit-per cell memory, according to a systematic or non-systematic ECC, are read and corrected (systematic ECC) or recovered (non-systematic ECC) in accordance with estimated probabilities that one or more of the read bits are erroneous. In one method of the present invention, the estimates are a priori. In another method of the present invention, the estimates are based only on aspects of the read bits that include significances or bit pages of the read bits. In a third method of the present invention, the estimates are based only on values of the read bits. Not all the estimates are equal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.