Apparatus and method for coding and decoding semi-systematic block low density parity check codes
US7526717B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jun 16, 2005 |
| Grant date | Apr 28, 2009 |
| Priority date | — |
| Expiry date | Dec 6, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/116
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for coding a semi-systematic block low density parity check (LDPC) code in which an information word is received and coded into a codeword including the information word, a first parity, a second parity, and a third parity, based on one of a first parity check matrix and a second parity check matrix, depending on a size to be applied when generating the information word into a semi-systematic block LDPC code. A part having a degree being at least equal to a predetermined degree is punctured from the information word, generating the semi-systematic block LDPC code. The semi-systematic block LDPC code includes the information word, the part of which was punctured, the first parity, the second parity, and the third parity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.