Narrow width metal oxide semiconductor transistor
US7528455B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 27, 2006 |
| Grant date | May 5, 2009 |
| Priority date | — |
| Expiry date | Feb 14, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/60
Abstract
Disclosed is a semiconductor transistor for enhancing performance of PMOS and NMOS transistors, particularly current driving performance, while reducing a narrow width effect. A narrow width MOS transistor includes: a channel of which width is W0 and length is L0; an active area including source and drain areas formed at both sides with the channel as a center; a gate insulating layer formed on the channel; a gate conductor formed on the gate insulating layer and intersecting the active area; a first additional active area of width is larger than that W0 of the channel as an active area added to the source area; and a second additional active area of width is larger than that W0 of the channel as an active area added to the drain area. When the structure of the transistor having the additional active areas is applied to NMOS and PMOS transistors, a driving current is represented as 107.27% and 103.31%, respectively. Accordingly, the driving currents of both PMOS and NMOS transistors are enhanced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.