Power pin to power pin electro-static discharge (ESD) clamp

US7529070B2 · kind B2 · utility

Assignee

• Agere Systems Inc. · US

Inventors

• Dipankar Bhattacharya · Macungie, US
• John C. Kriz · Palmerton, US
• Che Leung · Lower Saucon Township, US
• Duane J. Loeper · Spring City, US
• Yehuda Smooha · Allentown, US

Key dates

• Filing date: Mar 11, 2005
• Grant date: May 5, 2009
• Expiry date: Aug 8, 2025

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/811

Abstract

An ESD clamp circuit for use between separate power rails. An ESD clamp is based on a wide nMOSFET. A symmetrical circuit is designed vis-à-vis the two power rails, with respect to ground, allowing discharge of an ESD surge in both polarities of stress. An nMOSFET device drives the gate of a large nMOSFET (e.g., having a device width between 1000 and 10,000 microns). The large power rail-to-power rail nMOSFET has its gate controlled by the output inverter stage of either ESD detection circuit connected to a respective power supply rail. The gate is switched to a common ground during normal operation of the integrated circuit.