Generalized interlocked register cell (GICE)
US7529118B2 · kind B2 · utility
7Cited by
3References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 28, 2007 |
| Grant date | May 5, 2009 |
| Priority date | — |
| Expiry date | Oct 14, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4125
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory element which includes a family of fault-tolerant storage elements using complementary metal-oxide-semiconductor (CMOS) technology is provided. The memory element provides arbitrary levels of redundancy, allowing the tolerance of multiple single event upsets due to particle hits. The memory element may be used in memory arrays such as caches and register files, and clocked registers and latches found in data path and control structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.