Memory device and method thereof
US7529127B2 · kind B2 · utility
2Cited by
3References
28Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 28, 2006 |
| Grant date | May 5, 2009 |
| Priority date | — |
| Expiry date | Nov 28, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/5628
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device and method thereof are provided. The memory device may comprise a first buffer for receiving most significant bit (MSB) data and least significant bit (LSB) data to be stored within a memory cell; a second buffer for loading LSB data stored in the memory cell; and a data loader for generating at least one load signal based upon logic levels of the received MSB data in the first buffer and the loaded LSB data in the second buffer, the at least one load signal being configured to control programming permissions for the memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.