Scheduler, network processor, and methods for weighted best effort scheduling
US7529224B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 18, 2005 |
| Grant date | May 5, 2009 |
| Priority date | — |
| Expiry date | Jan 29, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L47/527
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Systems and methods for scheduling data packets in a network processor are disclosed. Embodiments provide a network processor that comprises a best-effort scheduler with a minimal calendar structure for addressing schedule control blocks. In one embodiment, a three-entry calendar structure provides for weighted best effort scheduling. Each of a plurality different flows has an associated schedule control block. Schedule control blocks are stored as linked lists in a last-in-first-out buffer. Each calendar entry is associated with a different linked list by storing in the calendar entry the address of the first-out schedule control block in the linked list. Each schedule control block has a counter and is assigned a weight according to the bandwidth priority of the flow to which the corresponding packet belongs. Each time a schedule control block is accessed from a last-in-first-out buffer storing the linked list, the scheduler generates a scheduling event and the counter of the schedule control block is incremented. When an incremented counter of a schedule control block equals its weight, the schedule control block is temporarily removed from further scheduling.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.