Interleaver
US7529307B2 · kind B2 · utility
7Cited by
3References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2005 |
| Grant date | May 5, 2009 |
| Priority date | — |
| Expiry date | Apr 24, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/27
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An interleaver and scheme for interleaving in which highly correlated bits are maximally separated. The scheme involves interleaving a set of bits to be delivered to a modulation system that utilizes a quantity of N carrier frequencies. A first block of N consecutive bits is assigned to each of N bins, on a one-bit-per-one-bin basis. The aforementioned assignment proceeds in a particular sequence. A second block of N consecutive bits is assigned to each of the N bins, on a one-bit-per-one-bin basis. The second block is assigned in the same sequence the first block was assigned. The second block is consecutive to the first block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.