Memory size allocation device and method for interleaving
US7529985B2 · kind B2 · utility
Inventors
Key dates
| Filing date | Jan 5, 2005 |
| Grant date | May 5, 2009 |
| Priority date | — |
| Expiry date | Aug 9, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/2732
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and device for interleaving the (N+1) input data and for allocating the corresponding memory comprises the steps of allocating a mth buffer section equals to (m×Dm+Pm) memory address for buffering the mth data of the N+1 input data, where m is a nonnegative integer from 0, 1 to N, Dm is the delay of the mth data, and Pm is a nature number representing a predetermined number of memory address for extra buffering the mth data; assigning an empty memory address in the mth buffer section to buffer the mth data; accessing the mth data from where the mth data buffered after buffering the (N+1) data, and outputting the (N+1) data in a (m×Dm) delay sequence. The present invention allocates the memory address effectively, so applying the present invention economizes the use of the memory request.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.