Optimized mapping of an integrated circuit design to multiple cell libraries during a single synthesis pass
US7530047B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 5, 2006 |
| Grant date | May 5, 2009 |
| Priority date | — |
| Expiry date | Oct 3, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit design synthesis method is provided comprising: associating a first cell library with a first block of a circuit design; associating a second cell library with a second block of the circuit design; specifying at least one constraint upon the overall circuit design; mapping a portion of the first block to a cell in the first cell library based upon the at least one constraint in view of a step of mapping a portion of the second block to a cell in the second cell library; and mapping a portion of the second block to a cell in the second cell library based upon the at least one constraint in view of the step of mapping a portion of the first block to a cell in the first cell library.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.