Vacuum wafer-level packaging for SOI-MEMS devices
US7531424B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | May 3, 2006 |
| Grant date | May 12, 2009 |
| Priority date | — |
| Expiry date | Jan 30, 2027 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB81C2203/0118
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A device and method for fabricating the device is disclosed. The device includes a substrate having an active layer disposed on a sacrificial layer. A trench is formed in the active layer to electrically isolate first and second regions in the active layer, and a non-conductive material is deposited on the substrate such that the non-conductive material fills the trench to form a substantially planar surface for support of further components of the device. In some cases, the non-conductive material fills only a portion of the trench sufficient to form the substantially planar surface. The non-conductive material may include silicon nitride.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.