Stacked semiconductor device
US7531905B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 10, 2007 |
| Grant date | May 12, 2009 |
| Priority date | — |
| Expiry date | Jan 10, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stacked semiconductor device includes an interposer substrate having external power supply terminals, and semiconductor chips stacked on the interposer substrate. A power supply wiring arranged in the semiconductor chip located in the bottom layer is connected to the external power supply terminal via a bump electrode, the power supply wiring arranged in the semiconductor chip located in the top layer is connected to the external power supply terminal via a bonding wire, and the power supply wirings each arranged in adjacent semiconductor chips are mutually connected via the through electrode. Such a loop structure can solve a problem such that the higher the semiconductor chip, the larger its voltage drop.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.