Analog amplifier having DC offset cancellation circuit and method of offset cancellation for analog amplifiers
US7532065B2 · kind B2 · utility
11Cited by
17References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 24, 2006 |
| Grant date | May 12, 2009 |
| Priority date | — |
| Expiry date | Oct 14, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45622
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An amplifier having DC offset compensation includes at least one input node and a pair of differential output nodes, a biasing circuit coupled to the input node; and a plurality of current sources. Selected ones of said current sources are coupled to the input node to adjust a DC voltage at the input node to provide DC offset compensation for the amplifier
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.