Memory device, circuits and methods for reading a memory device
US7532498B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 21, 2006 |
| Grant date | May 12, 2009 |
| Priority date | — |
| Expiry date | Nov 21, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/026
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A ferroelectric memory comprises a plurality of memory cells and circuitry to sense data thereof. Power supply decoupling circuitry may decouple supplies of the memory device during a portion of reading data. Additionally, ferroelectric domains of the memory cells may receive a series of polarization reversals to improve domain alignment and malleability. To drive reference cells of the memory with such polarization reversals, a multiplexer may be configured to swap a data bitline with a reference bitline so that reference cells may be accessed as regular data cells. While reading a ferroelectric memory, a self-timer circuit may monitor characteristics of the ferroelectric material and adjust an integration duration for a sense amplifier based on the monitored characteristics. A sampling-comparator may sample a signal related to the ferroelectric material at one instant, which may then be used subsequently thereafter by the self-timer circuit to influence an integration duration of the sense amplifier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.