Semiconductor memory device and control method of the same
US7532520B2 · kind B2 · utility
15Cited by
5References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 16, 2007 |
| Grant date | May 12, 2009 |
| Priority date | — |
| Expiry date | Nov 20, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a memory cell array, a voltage generating circuit, a memory circuit which stores a reference pulse number of an erase voltage of the memory cell array and a parameter, and a control circuit which controls, when a pulse number of the erase voltage exceeds the reference pulse number of the erase voltage, the voltage generating circuit in a manner to increase at least an erase verify level in accordance with the parameter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.