Method and circuit for increasing the memory access speed of an enhanced synchronous memory
US7533231B1 · kind B1 · utility
Inventors
Key dates
| Filing date | Oct 13, 2004 |
| Grant date | May 12, 2009 |
| Priority date | — |
| Expiry date | Oct 13, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2245
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory and method for operating it provide for increased data access speed. In an implementation, a synchronous memory or SDRAM includes a central memory region with memory blocks arranged in sets on respective opposite sides. A number of primary sense amplifier sets are provided, each set being associated with a respective set of the memory blocks and located adjacent. A row cache is provided in the central memory region, and row decoders decode a row address in response to a “bank activate” command and move data from a decoded row address into a primary sense amplifier set associated with a memory block containing the decoded row address and into the row cache, before application of a “read” command to the SDRAM. Column decoders decode a column address in response to a “read” command and for reading data from the cache in accordance with the decoded column address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.