Automatic operand load, modify and store
US7533250B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 25, 2005 |
| Grant date | May 12, 2009 |
| Priority date | — |
| Expiry date | Oct 10, 2026 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor comprising a decode logic coupled to a first storage unit and comprising a data structure. The processor also comprises a second storage unit coupled to the decode logic. The decode logic obtains a single instruction from the first storage unit and, if indicated by a first bit in the data structure, processes a group of instructions in lieu of the single instruction, where the single instruction requires an operand. If indicated by a second bit in the data structure, the decode logic obtains the operand from the first storage unit, modifies the operand, and stores the operand to the second storage unit for use by the group of instructions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.