Patent · US Active

Systems and methods for CPU repair

US7533293B2 · kind B2 · utility

3Cited by

14References

8Claims

0Family size

Assignee

HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. · US

Inventors

Jeff Barlow · Roseville, US
Jeff Brauch · Fort Collins, US
Howard Calkin · Davis, US
Raymond Gratias · Fort Collins, US
Stephen Hack · Fort Collins, US
Lacey Joyal · Fort Collins, US
Guy Kuntz · Chico, US
Ken Pomaranski · Roseville, US
Michael Sedmak · Fort Collins, US

Key dates

Filing date	Feb 17, 2006
Grant date	May 12, 2009
Priority date	—
Expiry date	Apr 27, 2027

Classification

Technology area (CPC G)Physics
CPC primaryG11C29/76
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

In one embodiment, a CPU cache management system is provided. The CPU management system includes, for example, a CPU chip and cache management logic. The CPU chip include cache elements that are initially in use and spare cache elements that not initially in use. The cache management logic determines whether currently-used cache elements are faulty. If a cache element is determined to be faulty, the cache management logic schedules a reboot of the computer and swaps in a spare cache element for the faulty currently-used cache element during the reboot.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.