Functional coverage driven test generation for validation of pipelined processors
US7533294B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 9, 2005 |
| Grant date | May 12, 2009 |
| Priority date | — |
| Expiry date | Jan 19, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3323
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A functional coverage based test generation technique for pipelined architectures is presented. A general graph-theoretic model is developed that can capture the structure and behavior (instruction-set) of a wide variety of pipelined processors. A functional fault model is developed and used to define the functional coverage for pipelined architectures. Test generation procedures are developed that accept the graph model of the architecture as input and generate test programs to detect all the faults in the functional fault model. A graph model of the pipelined processor is automatically generated from the specification using functional abstraction. Functional test programs are generated based on the coverage of the pipeline behavior. Module level property checking is used to reduce test generation time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.