Configurable error handling apparatus and methods to operate the same
US7533300B2 · kind B2 · utility
6Cited by
2References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 13, 2006 |
| Grant date | May 12, 2009 |
| Priority date | — |
| Expiry date | May 8, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/0781
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Configurable error handling apparatus and methods to operate the same are disclosed. An example apparatus comprises a processor core in a semiconductor package, a hardware functional block in the semiconductor package, an error handler in the semiconductor package, wherein the error handler is configurable to route error data from the hardware functional block to at least one of a first error log or a second error log and to route error signals from the hardware functional block to at least one of an operating system or firmware, and wherein the processor core configures the error handler and the hardware functional block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.