SRAM memory cell protected against current or voltage spikes
US7535743B2 · kind B2 · utility
3Cited by
4References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 12, 2005 |
| Grant date | May 19, 2009 |
| Priority date | — |
| Expiry date | Mar 8, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/005
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell is protected against current or voltage spikes. The cell includes a group of redundant data storage nodes for the storage of information in at least one pair of complementary nodes. The cell further includes circuitry for restoring information to its initial state following a current or voltage spike which modifies the information in one of the nodes of the pair using the information stored in the other node. The data storage nodes of each pair in the cell are implanted on opposite sides of an opposite conductivity type well from one another within a region of a substrate defining the boundaries of the memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.