Transmitter circuit, receiver circuit, clock data recovery phase locked loop circuit, data transfer method and data transfer system
US7535957B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 13, 2005 |
| Grant date | May 19, 2009 |
| Priority date | — |
| Expiry date | Dec 3, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K7/10
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
[Problems] To realize a reliable and stable transfer of digital data that does not require a reference clock and a handshake operation.[Means for Solving the Problem] The present invention provides a digital data transfer method for alternately and periodically transferring first information and second information respectively in a first period and in a second period, wherein: an amount of information of the first information per unit time in the first period is greater than an amount of information of the second information per unit time in the second period; and the second information in the first period is transferred as pulse-width-modulated serial data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.