Method and apparatus for determining a dynamic random access memory page management implementation
US7536530B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2005 |
| Grant date | May 19, 2009 |
| Priority date | — |
| Expiry date | Dec 30, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0215
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for a processor to determine a memory page management implementation used by a memory controller without necessarily having direct access to the circuits or registers of the memory controller is disclosed. In one embodiment, a matrix of counters correspond to potential page management implementations and numbers of pages per block. The counters may be incremented or decremented depending upon whether the corresponding page management implementations and numbers of pages predict a page boundary whenever a long access latency is observed. The counter with the largest value after a period of time may correspond to the actual page management implementation and number of pages per block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.