Patent · US Active

Logic analyzer systems and methods for programmable logic devices

US7536615B1 · kind B1 · utility

12Cited by

16References

20Claims

0Family size

Assignee

Lattice Semiconductor Corporation · US

Inventors

David A. Pierce · Wheaton, US
Michael Hammer · Westchester, US
Brian M. Caslis · Wilsonville, US

Key dates

Filing date	Mar 26, 2007
Grant date	May 19, 2009
Priority date	—
Expiry date	Jan 30, 2028

Classification

Technology area (CPC G)Physics
CPC primaryG01R31/3177
WIPO fieldMeasurement
WIPO sectorInstruments

Abstract

A programmable logic device includes, in accordance with one embodiment, a plurality of logic blocks; an interconnect structure adapted to route signals among the logic blocks; and a memory for storing data within the programmable logic device. A first set of the logic blocks are configured as logic analyzer trigger units adapted to each receive one or more input signals from within the programmable logic device and provide a corresponding trigger unit output signal. A portion of the memory stores a logic analyzer trigger expression, with the trigger unit output signals provided to the memory as address signals for the trigger expression.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.