Low temperature method for fabricating high-aspect ratio vias and devices fabricated by said method

US7538032B2 · kind B2 · utility

Assignee

• TELEDYNE SCIENTIFIC & IMAGING, LLC · US

Inventors

• Robert L. Borwick, III · Thousand Oaks, US
• Philip A. Stupar · Oxnard, US
• Jeffrey F. DeNatale · Thousand Oaks, US
• Chailun Tsai · Thousand Oaks, US
• Zhimin Jamie Yao · Dallas, US
• Kathleen Garrett · Calabasas, US
• John T. White · Gilbert, US
• Les Warren · Thousand Oaks, US
• Morgan Tench · Camarillo, US

Key dates

• Filing date: Jun 23, 2005
• Grant date: May 26, 2009
• Expiry date: Dec 11, 2025

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/0002
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Embodiments of the present invention are directed to a process for forming small diameter vias at low temperatures. In preferred embodiments, through-substrate vias are fabricated by forming a through-substrate via; and depositing conductive material into the via by means of a flowing solution plating technique, wherein the conductive material releases a gas that pushes the conductive material through the via to facilitate plating the via with the conductive material. In preferred embodiments, the fabrication of the substrate is conducted at low temperatures.