Standard cell, standard cell library, and semiconductor integrated circuit with suppressed variation in characteristics
US7538368B2 · kind B2 · utility
123Cited by
1References
12Claims
0Family size
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Key dates
| Filing date | May 31, 2005 |
| Grant date | May 26, 2009 |
| Priority date | — |
| Expiry date | Aug 30, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/931
Abstract
In a standard cell, at least one of transistors on either side of a transistor having gate length different from that of the other transistors are set to be always in the OFF state. This prevents influence to the operation of the standard cell even with variation in final gate dimension, suppressing variation in characteristics of the standard cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.