Transparent field reconfiguration for programmable logic devices
US7538574B1 · kind B1 · utility
6Cited by
23References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 5, 2005 |
| Grant date | May 26, 2009 |
| Priority date | — |
| Expiry date | Jan 8, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1776
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In accordance with an embodiment of the present invention, a programmable logic device (PLD, such as a field programmable gate array (FPGA)) includes a plurality of input/output blocks having boundary scan cells that are adapted to precondition registers within a logic area of the programmable logic device with desired signal values prior to release of control of the input/output blocks to user-defined logic provided by a reconfiguration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.