DC offset canceling circuit
US7538595B2 · kind B2 · utility
2Cited by
1References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 8, 2007 |
| Grant date | May 26, 2009 |
| Priority date | — |
| Expiry date | Oct 16, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/375
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention provides a $ for canceling DC offset, comprising: a first circuit accumulating a first square value of a plurality of signal values in a time period; a second circuit calculation a second square value of an accumulation of said signal values in said time period, wherein said square value is divided by a quantity of said signal values in said time period to generate a DC offset value; and a third circuit, connected to said first circuit and second circuit, calculating a difference between said first square value and said DC offset value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.