Offset cancellation and reduced source induced 1/f noise of voltage reference by using bit stream from over-sampling analog-to-digital converter
US7538705B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 18, 2007 |
| Grant date | May 26, 2009 |
| Priority date | — |
| Expiry date | Jul 18, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/422
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An over-sampling analog-to-digital converter (ADC) uses a chopper stabilized voltage reference with improved reference voltage offset cancellation and reduced source induced 1/f noise. The chopper stabilized voltage reference receives chopper clocks that have been correlated with the serial bitstream produced by the sigma-delta modulator of the ADC. The chopper clocks are generated so that the reference voltage produces for each distinct bitstream level an independent sequence of voltages that comprise alternatively positive and negative voltage reference offset contributions. After integration (averaging) is performed within the sigma-delta modulator, these equal and opposite reference offset contributions cancel out regardless of the bit pattern comprising the bitstream.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.