PVT optimization architecture for always-on GPS receivers
US7538726B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 10, 2007 |
| Grant date | May 26, 2009 |
| Priority date | — |
| Expiry date | Apr 10, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01S19/34
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method to reduce power consumption in a device is disclosed. The method generally includes the steps of (A) generating a plurality of pseudorange signals by tracking a plurality of position signals received from a plurality of satellites in a positioning system, at least one of the position signals from each one of the satellites respectively, (B) calculating both an initial position and an initial time bias from the pseudorange signals using a processing capability of the device at a normal capacity and (C) calculating both an updated position and an updated time bias using the processing capability reduced to a first capacity, wherein the first capacity (i) consumes less power than the normal capacity and (ii) is suitable to process the updated position and the updated time bias using a limited number comprising less than all of the pseudorange signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.