Semiconductor device with a relief processing portion
US7539071B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 31, 2007 |
| Grant date | May 26, 2009 |
| Priority date | — |
| Expiry date | Aug 9, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/806
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Each of a plurality of redundant memories includes a plurality of memory cells and is operable to be relieved when a defective cell exists. This plurality of redundant memories can operate independently of each other. A relief processing portion is shared by this plurality of redundant memories. A test circuit inspects the plurality of redundant memories. When the test circuit determines that a defective cell exists, the test circuit outputs relief information to relieve the defective cell. The relief processing portion has a plurality of defect relief portions each having a relief information storage portion operable to store the relief information and performs the processing of relieving the plurality of redundant memories.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.