Overshoot reduction in VCO calibration for serial link phase lock loop (PLL)
US7539473B2 · kind B2 · utility
2Cited by
8References
8Claims
0Family size
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Key dates
| Filing date | Apr 26, 2006 |
| Grant date | May 26, 2009 |
| Priority date | — |
| Expiry date | Jul 20, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0891
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit design, method, and system for tracking VCO calibration without requiring an over-designed divider as in conventional implementation. A filter reset component is added to the inputs of the VCO. A process step is added to the calibration mechanism/process that shorts the filter nodes and thus centers the frequency of the VCO before stepping from one frequency band to the next.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.