System and method for packet processor status monitoring
US7539750B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2004 |
| Grant date | May 26, 2009 |
| Priority date | — |
| Expiry date | Nov 20, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed herein are a system and method for status monitoring, including debug error detection, during data packet processing. In general terms, the system for status monitoring during data packet processing can be implemented as a system including a packet processor and a buffer. The packet processor generates processing data based on one or more control structures while revising packet data. The packet processor generates the processing data while performing one or more lookup cycles. The buffer records the processing data and the status of the one or more control structures. The processing data includes a lookup number and the lookup number identifies the number of cycles performed by the packet processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.