System, method and storage medium for providing segment level sparing
US7539800B2 · kind B2 · utility
93Cited by
194References
5Claims
0Family size
Assignee
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Key dates
| Filing date | Jul 30, 2004 |
| Grant date | May 26, 2009 |
| Priority date | — |
| Expiry date | Jul 30, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/104
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory subsystem that includes segment level sparing. The memory subsystem includes a cascaded interconnect system with segment level sparing. The cascaded interconnect system includes two or more memory assemblies and a memory bus. The memory bus includes multiple segments and the memory assemblies are interconnected via the memory bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.